Speeding up the Discrete Cosine Transform Through Custom Operations and Fixed-Point Arithmetic
Küçük Resim Yok
Tarih
2025
Yazarlar
Dergi Başlığı
Dergi ISSN
Cilt Başlığı
Yayıncı
Bursa Teknik Üniversitesi
Erişim Hakkı
info:eu-repo/semantics/openAccess
Özet
Digital signal processing applications are becoming increasingly important because modern systems work with much larger amounts of data than before. The Discrete Cosine Transform (DCT), used in almost all multimedia compression methods, creates a significant computational load especially in resource-constrained embedded systems. This study proposes four custom operations compatible with Transport-Triggered Architecture (TTA). To enhance computational efficiency and avoid floating-point overhead, fixed-point arithmetic is used. To analyse the effect of the proposed operations, different Application-Specific Instruction Set Processor (ASIP) configurations were created on a general-purpose processor architecture. Performance analyses show that speedups between 2x and 3.5x are achieved. In addition, the developed processor models have been implemented in hardware. FPGA synthesis results indicate a reasonable increase in chip area, showing that the proposed solutions could be an efficient alternative, particularly for limited-resource embedded systems.
Açıklama
2023/69002-01
Anahtar Kelimeler
Image Processing, Görüntü İşleme [EN] Digital Processor Architectures, Dijital İşlemci Mimarileri
Kaynak
Journal of Innovative Science and Engineering
WoS Q Değeri
Scopus Q Değeri
Cilt
9
Sayı
2
